Semiconductor device is widely adopted in various applications. The geometry is trending down rapidly as user's demands increases on the performance and functionality. For example, a 3G mobile phone presented in the market is expected to be capable of telecommunicating, capturing images and processing high stream data. In order to fulfill the requirements, the 3G mobile phone needs to be equipped with different devices such as a processor, a memory and an image sensor in a limited space.
Combining several semiconductor devices in one package is one of the approaches to enhance the performance by integrating devices with various functions into a single component. Roadmap in the field shows a three dimensional package with a multi-level structure for a superior and miniature sized semiconductor component.
A three dimensional integrated semiconductor package contains several different sub-structures. The sub-structures are arranged in a stack manner and are either in contact with each other or linked by interconnects. However, on the other hand, different properties of the sub-structures also create challenges to a designer. Compared to a two dimensional semiconductor package, failure modes increase for a comparatively more complex three dimensional integrated semiconductor package. As such, improvements in the structure and method for a three dimensional semiconductor package continue to be sought.